1. Field of the Invention
This invention relates to microelectronic devices and related fabrication methods. More particularly, this invention relates to a memory device having a digit line that is directly coupled to a transistor source.
2. Description of the Related Art
Since the introduction of the digital computer, electronic storage devices have been a vital resource for the retention of data. Conventional semiconductor electronic storage devices, such as Dynamic Random Access Memory (DRAM), typically incorporate capacitor and transistor structures in which the capacitors temporarily store data based on the charged state of the capacitor structure. In general, this type of semiconductor Random Access Memory (RAM) often requires densely packed capacitor structures that are easily accessible for electrical interconnection.
A DRAM cell typically comprises a charge storage capacitor (or cell capacitor) coupled to an access device, such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET, or simply FET). These access devices functions to apply or remove charge on the capacitor, thus affecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is determined by the electrode (or storage node) area and the interelectrode spacing. The conditions of DRAM operation such as operating voltage, leakage rate and refresh rate, will generally mandate that a certain minimum charge be stored by the capacitor.
FETs are widely used in integrated circuit devices including logic, memory and/or microprocessor devices that are used in consumer and/or industrial applications. As the integration density of integrated circuit FETs continues to increase, it may be desirable to continue to shrink the dimensions of the FETs. Conventionally, features of integrated circuit FETs may be formed on a microelectronic substrate, such as silicon semiconductor substrate, using photolithography and etching. As the minimum feature size is reduced, conventional fabrication techniques must also evolve in order to accurately fabricate the reduced size features. In some embodiments, fabrication of memory devices may be improved by reducing the number of processing steps involved in the fabrication process. In addition, improved transistor and charge storage devices may also decrease the manufacturing complexity, while maintaining or increasing the accuracy of the manufacturing process.